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1/52 preliminary data august 2002 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. m58mr032c m58mr032d 32 mbit (2mb x16, mux i/o, dual bank, burst) 1.8v supply flash memory n supply voltage Cv dd = v ddq = 1.7v to 2.0v for program, erase and read Cv pp = 12v for fast program (optional) n multiplexed address/data n synchronous / asynchronous read C burst mode read: 40mhz C page mode read (4 words page) C random access: 100ns n programming time C 10s by word typical C two or four words programming option n memory blocks C dual bank memory array: 8/24 mbit C parameter blocks (top or bottom location) n dual operations C read within one bank while program or erase within the other C no delay between read and write operations n protection/security C all blocks protected at power-up C any combination of blocks can be protected C 64 bit unique device identifier C 64 bit user programmable otp cells C one parameter block permanently lockable n common flash interface (cfi) n 100,000 program/erase cycles per block n electronic signature C manufacturer code: 20h C top device code, m58mr032c: 88dah C bottom device code, m58mr032d: 88dbh fbga tfbga48 (zc) 10 x 4 ball array figure 1. logic diagram ai90019 5 a16-a20 w adq0-adq15 v dd m58mr032c m58mr032d e v ss 16 g rp wp v ddq v pp l k wait binv
m58mr032c, m58mr032d 2/52 figure 2. tfbga connections (top view through package) ai90020 v ddq adq10 adq11 adq4 adq5 v ss adq14 adq15 h adq9 adq2 adq3 adq6 adq7 v ss g a18 wp rp binv l a20 a16 v ddq f a19 v pp w v dd k wait e 8 7 6 5 4 3 2 1 adq1 adq8 e a17 adq0 g 10 9 adq13 adq12 v ss v ss d c b a du du du du 12 11 du du du du 14 13 nc nc description the m58mr032 is a 32 mbit non-volatile flash memory that may be erased electrically at block level and programmed in-system on a word-by- word basis using a 1.7v to 2.0v v dd supply for the circuitry. for program and erase operations the necessary high voltages are generated internally. the device supports synchronous burst read and asynchronous read from all the blocks of the mem- ory array; at power-up the device is configured for page mode read. in synchronous burst mode, a new data is output at each clock cycle for frequen- cies up to 40mhz. the array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. all blocks are protected against pro- gramming and erase at power-up. blocks can be unprotected to make changes in the application and then re-protected. a parameter block "security block" can be perma- nently protected against programming and erasing in order to increase the data security. an optional 12v v pp power supply is provided to speed up the program phase at costumer production. an inter- nal command interface (c.i.) decodes the instruc- tions to access/modify the memory content. the program/erase controller (p/e.c.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. two status registers indicate the state of each bank. instructions for read array, read electronic sig- nature, read status register, clear status regis- ter, write read configuration register, program, block erase, bank erase, program suspend, pro- gram resume, erase suspend, erase resume, block protect, block unprotect, block locking, protection program, cfi query, are written to the memory through a command interface (c.i.) using standard micro-processor write timings. the memory is offered in tfbga48, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to 1).
3/52 m58mr032c, m58mr032d table 1. signal names a16-a20 address inputs adq0-adq15 data input/outputs or address inputs, command inputs e chip enable g output enable w write enable rp reset/power-down wp write protect k burst clock l latch enable wait wait data in burst mode binv bus invert v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground du dont use as internally connected nc not connected internally organization the m58mr032 is organized as 2mb by 16 bits. the first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus adq0-adq15. the remaining address lines a16-a20 are the msb addresses. chip enable e , output enable g and write enable w inputs provide memory control. the clock k input synchronizes the memory to the microprocessor during burst read. reset rp is used to reset all the memory circuitry and to set the chip in power-down mode if a proper setting of the read configuration register en- ables this function. wait output indicates to the microprocessor the status of the memory during the burst mode oper- ations. memory blocks the device features asymmetrically blocked archi- tecture. m58mr032 has an array of 71 blocks and is divided into two banks a and b, providing dual bank operations. while programming or erasing in bank a, read operations are possible into bank b or vice versa. only one bank at the time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the memory features an erase suspend allowing reading or programming in another block. once suspended the erase can be resumed. program can be suspended to read data in another block and then resumed. the bank size and sectoriza- tion are summarized in table 3. parameter blocks are located at the top of the memory address space for the m58mr032c, and at the bottom for the m58mr032d. the memory maps are shown in figure 3. table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. depends on range. 3. minimum voltage may undershoot to C2v during transition and for less than 20ns. symbol parameter value unit t a ambient operating temperature (2) C40 to 85 c t bias temperature under bias C40 to 125 c t stg storage temperature C55 to 155 c v io (3) input or output voltage C0.5 to v ddq +0.5 v v dd , v ddq supply voltage C0.5 to 2.7 v v pp program voltage C0.5 to 13 v
m58mr032c, m58mr032d 4/52 the architecture includes a 128 bits protection register that is divided into two 64-bits segments. in the first one is written a unique device number, while the second one is programmable by the us- er. the user programmable segment can be per- manently protected programming the bit 1 of the protection lock register (see protection register and security block). the parameter block (# 0) is a security block. it can be permanently protected by the user programming the bit 2 of the protection lock register. block protection against program or erase pro- vides additional data security. all blocks are pro- tected and unlocked at power-up. instructions are provided to protect or un-protect any block in the application. a second register locks the protection status while wp is low (see block locking descrip- tion). table 3. bank size and sectorization bank size parameter blocks main blocks bank a 8 mbit 8 blocks of 4 kword 15 blocks of 32 kword bank b 24 mbit - 48 blocks of 32 kword figure 3. memory map ai90069 512 kbit or 32 kword 000000h 007fffh 512 kbit or 32 kword 1f0000h 1f7fffh top boot block address lines a20-a0 512 kbit or 32 kword 178000h 17ffffh total of 48 main blocks 512 kbit or 32 kword 180000h 187fffh 64 kbit or 4 kword 1ff000h 1fffffh 64 kbit or 4 kword 1f8000h 1f8fffh total of 15 main blocks total of 8 parameter blocks bank b bank a 64 kbit or 4 kword 000000h 000fffh 512 kbit or 32 kword 078000h 07ffffh bottom boot block address lines a20-a0 64 kbit or 4 kword 007000h 007fffh total of 8 parameter blocks 512 kbit or 32 kword 008000h 00ffffh 512 kbit or 32 kword 1f8000h 1fffffh 512 kbit or 32 kword 080000h 087fffh total of 15 main blocks total of 48 main blocks bank b bank a
5/52 m58mr032c, m58mr032d signal descriptions see figure 1 and table 1. address inputs or data input/output (adq0- adq15). when chip enable e is at v il and out- put enable g is at v ih the multiplexed address/ data bus is used to input addresses for the memo- ry array, data to be programmed in the memory ar- ray or commands to be written to the c.i. the address inputs for the memory array are latched on the rising edge of latch enable l . the address latch is transparent when l is at v il . in synchro- nous operations the address is also latched on the first rising/falling edge of k (depending on clock configuration) when l is low. both input data and commands are latched on the rising edge of write enable w . when chip enable e and output en- able g are at v il the address/data bus outputs data from the memory array, the electronic signa- ture manufacturer or device codes, the block pro- tection status the read configuration register status, the protection register or the status regis- ter. the address/data bus is high impedance when the chip is deselected, output enable g is at v ih , or rp is at v il . address inputs (a16-a20). the five msb ad- dresses of the memory array are latched on the rising edge of latch enable l . in synchronous op- eration these inputs are also latched on the first rising/falling edge of k (depending on clock config- uration) when l is low. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e at v ih deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at v il . output enable (g ). the output enable gates the outputs through the data buffers during a read op- eration. when g is at v ih the outputs are high im- pedance. write enable (w ). this input controls writing to the command register and data latches. data are latched on the rising edge of w . write protect (wp ). this input gives an addition- al hardware protection level against program or erase when pulled at v il , as described in the block lock instruction description. reset/power-down input (rp ). the rp input provides hardware reset of the memory, and/or power-down functions, depending on the read configuration register status. reset/power-down of the memory is achieved by pulling rp to v il for at least t plph . when the reset pulse is given, the memory will recover from power-down (when en- abled) in a minimum of t phel , t phll or t phwl (see table 31 and figure 15) after the rising edge of rp . exit from reset/power-down changes the contents of the read configuration register bits 14 and 15, setting the memory in asynchronous page mode read and power save function dis- abled. all blocks are protected and unlocked after a reset/power-down. latch enable (l ). l latches the address bits adq0-adq15 and a16-a20 on its rising edge. the address latch is transparent when l is at v il and it is inhibited when l is at v ih . clock (k). the clock input synchronizes the memory to the micro controller during burst mode read operation; the address is latched on a k edge (rising or falling, according to the configuration set- tings) when l is at v il . k is don't care during asyn- chronous page mode read and in write operations. wait (wait ). wait is an output signal used dur- ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. this output is high impedance when e or g are high or rp is at v il , and can be configured to be active during the wait cycle or one clock cy- cle in advance. bus invert (binv). binv is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. the power saving is achieved by inverting the data output on adq0-adq15 every time this gives an advantage in terms of number of toggling bits. in burst mode read, each new data output from the memory is compared with the previous data. if the number of transitions required on the data bus is in excess of 8, the data is inverted and the binv signal will be driven by the memory at v oh to inform the receiv- ing system that data must be inverted before any further processing. by doing so, the actual transi- tions on the data bus will be less than 8. in a similar way, when a command is given, binv may be driven by the system at v ih to inform the memory that the data input must be inverted. like the other input/output pins, binv is high im- pedance when the chip is deselected, output en- able g is at v ih or rp is at v il ; when used as an input, binv must follow the same set-up and hold timings of the data inputs. v dd and v ddq supply voltage (1.7v to 2.0v). v dd is the main power supply for all operations (read, program and erase). v ddq is the supply voltage for input and output.
m58mr032c, m58mr032d 6/52 v pp program supply voltage (12v). v pp is both a control input and a power supply pin. the two functions are selected by the voltage range ap- plied to the pin; if v pp is kept in a low voltage range (0 to 2v) v pp is seen as a control input, and the current absorption is limited to 5a (0.2a typical). in this case with v pp = v il we obtain an absolute protection against program or erase; with v pp = v pp1 these functions are enabled (see table 26). v pp value is only sampled during program or erase write cycles; a change in its value after the operation has been started does not have any ef- fect and program or erase are carried on regularly. if v pp is used in the 11.4v to 12.6v range (v pph ) then the pin acts as a power supply (see table 26). this supply voltage must remain stable as long as program or erase are running. in read mode the current sunk is less then 0.5ma, while during program and erase operations the current may increase up to 10ma. v ss ground. v ss is the reference for all the volt- age measurements.
7/52 m58mr032c, m58mr032d table 4. user bus operations (1) note: 1. x = don't care. table 5. read electronic signature (as and read cfi instructions) (1) note: 1. addresses are latched on the rising edge of l input. 2. ea means electronic signature address (see read electronic signature) 3. value during address latch. table 6. read block protection (as and read cfi instructions) (1) note: 1. addresses are latched on the rising edge of l input. 2. a locked block can be unprotected only with wp at v ih. 3. value during address latch. 4. ba means block address. first cycle command address should indicate the bank of the block address. operation e g w l rp wp adq15-adq0 address latch v il v ih v ih v il (rising edge) v ih v ih address input write v il v ih v il v ih v ih v ih data input output disable v il v ih v ih v ih v ih v ih hi-z standby v ih xx x v ih x hi-z reset / power-down x x x x v il x hi-z block locking v il xx x v ih v il x code device e g w adq1 (3) adq0 (3) other address (2) adq15-0 manufacturer code v il v il v ih v il v il ea (2) 0020h device code m58mr032c v il v il v ih v il v ih ea (2) 88dah m58mr032d v il v il v ih v il v ih ea (2) 88dbh block status e g w adq1 (3) adq0 (3) other address adq15-0 protected and unlocked v il v il v ih v ih v il ba (4) 0001 unprotected and unlocked v il v il v ih v ih v il ba (4) 0000 protected and locked v il v il v ih v ih v il ba (4) 0003 unprotected and locked (2) v il v il v ih v ih v il ba (4) 0002 device operations the following operations can be performed using the appropriate bus cycles: address latch, read array (random, and page modes), write com- mand, output disable, standby, reset/power- down and block locking. see table 4. address latch. in asynchronous operation, the address is latched on the rising edge of l input. in burst mode the address is latched either on the ris- ing edge of l or on the first rising/falling edge of k (depending on configuration settings) when l is low. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register, the cfi, the block protection status, the read configuration regis- ter status and the protection register. read operation of the memory array may be per- formed in asynchronous page mode or synchro- nous burst mode. in asynchronous page mode data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by adq0 and adq1 address inputs. according to the device configuration the following read operations: electronic signature - status register - cfi - block protection status - read configuration register status - protection regis- ter must be accessed as asynchronous read or as single synchronous read (see figure 4).
m58mr032c, m58mr032d 8/52 table 7. read protection register (rsig and rcfi instruction) (1) note: 1. addresses are latched on the rising edge of l input. 2. x = don't care. table 8. dual bank operations (1, 2, 3) note: 1. for detailed description of command see table 33 and 34. 2. there is a status register for each bank; status register indicates bank state, not p/e.c. status. 3. command must be written to an address within the block targeted by that command. word e g w a20-17 adq15-8 adq7-0 adq15-8 adq7-3 adq2 adq1 adq0 lock v il v il v ih x (2) x (2) 80h 00h 00000b security prot.data otp prot.data 0 unique id 0 v il v il v ih x (2) x (2) 81h id data id data id data id data id data unique id 1 v il v il v ih x (2) x (2) 82h id data id data id data id data id data unique id 2 v il v il v ih x (2) x (2) 83h id data id data id data id data id data unique id 3 v il v il v ih x (2) x (2) 84h id data id data id data id data id data otp 0 v il v il v ih x (2) x (2) 85h otp data otp data otp data otp data otp data otp 1 v il v il v ih x (2) x (2) 86h otp data otp data otp data otp data otp data otp 2 v il v il v ih x (2) x (2) 87h otp data otp data otp data otp data otp data otp 3 v il v il v ih x (2) x (2) 88h otp data otp data otp data otp data otp data status of one bank commands allowed in the other bank read array read status read id/cfi program erase/ erase resume program suspend erase suspend protect unprotect idle yes yes yes yes yes yes yes yes reading CCCCCCCC programming yes yes yes C C C C yes erasing yes yes yes C C C C yes program suspended ye s ye s ye s C C C C ye s erase suspended yes yes yes yes C yes C yes
9/52 m58mr032c, m58mr032d figure 4. single synchronous read sequence (rsig, rcfi, rsr instructions) ai90022 a20-a16 valid address l adq15-adq0 valid address valid data not valid adq15-adq0 valid address valid data adq15-adq0 valid address not valid not valid not valid configuration code 4 configuration code 3 conf. code 2 not valid not valid valid data k both chip enable e and output enable g must be at v il in order to read the output of the memory. read array is the default state of the device when exiting power down or after power up. burst read. the device also supports a burst read. in this mode a burst sequence is started at the first clock edge (rising or falling according to configuration settings) after the falling edge of l . after a configurable delay of 2 to 5 clock cycles a new data is output at each clock cycle. the burst sequence may be configured for linear or inter- leaved order and for a length of 4, 8 words or for continuous burst mode. wrap and no-wrap modes are also supported. a wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. see the write read configuration reg- ister (cr) instruction for more details on all the possible settings for the synchronous burst read (see table 14). it is possible to perform burst read across bank boundary (all banks in read array mode). write. write operations are used to give instruc- tion commands to the memory or to latch input data to be programmed. a write operation is initi- ated when chip enable e and write enable w are at v il with output enable g at v ih . addresses are latched on the rising edge of l . commands and in- put data are latched on the rising edge of w or e whichever occurs first. noise pulses of less than 5ns typical on e , w and g signals do not start a write cycle. write operations are asynchronous and clock is ignored during write. dual bank operations. the dual bank allows to run different operations simultaneously in the two banks. it is possible to read array data from one bank while the other is programming, erasing or reading any data (cfi, status register or electronic signature). read and write cycles can be initiated for simulta- neous operations in different banks without any delay. only one bank at a time is allowed to be in program or erase mode, while the other must be in one of the read modes (see table 8). commands must be written to an address within the block targeted by that command. output disable. the data outputs are high im- pedance when the output enable g is at v ih with write enable w at v ih . standby. the memory is in standby when chip enable e is at v ih and the p/e.c. is idle. the pow- er consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. automatic standby. when in read mode, after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically en- ters a pseudo-standby mode where consumption is reduced to the cmos standby value, while out- puts still drive the bus. the automatic standby fea- ture is not available when the device is configured for synchronous burst mode.
m58mr032c, m58mr032d 10/52 reset/power-down. the memory is in power- down when the read configuration register is set for power-down and rp is at v il . the power con- sumption is reduced to the power-down level, and outputs are in high impedance, independent of the chip enable e , output enable g or write enable w inputs. the memory is in reset when the read configuration register is set for reset and rp is at vil . the power consumption is the same of the standby and the outputs are in high impedance. after a reset/power down the device defaults to read array mode, the status register is set to 80h and the read configuration register defaults to asynchronous read. block locking. any combination of blocks can be temporarily protected against program or erase by setting the lock register and pulling wp to v il . the following summarizes the locking oper- ation. all blocks are protected on power-up. they can then be unprotected or protected with the un- protect and protect commands. the lock com- mand protects a block and prevents it from being unlocked when wp = 0. when wp = 1, lock is overridden. lock is cleared only when the device is reset or powered-down (see protect instruction). table 9. identifier codes note: 1. drc means die revision code. cr means read configuration register. lpr means lock protection register. pr means unique device number and user programmable otp. code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 88da bottom bank address + 01 88db block protection protected and unlocked bank address + 02 0001 unprotected and unlocked 0000 protected and locked 0003 unprotected and locked 0002 die revision code bank address + 03 drc (1) read configuration register bank address + 05 cr (1) lock protection register bank address + 80 lpr (1) protection register bank address + 81 bank address + 88 pr (1)
11/52 m58mr032c, m58mr032d table 10. commands hex code command 00h invalid reset 01h protect confirm 03h write read configuration register confirm 10h alternative program set-up 20h block erase set-up 2fh lock confirm 30h double word program set-up 40h program set-up 50h clear status register 55h tetra word program set-up 60h protect set-up and write read configuration register 70h read status register 80h bank erase set-up 90h read electronic signature 98h cfi query b0h program/erase suspend c0h protection program and lock protection program d0h program/erase resume, erase confirm or unprotect confirm ffh read array instructions and commands eighteen instructions are available (see tables 10 and 11) to perform read memory array, read sta- tus register, read electronic signature, cfi que- ry, block erase, bank erase, program, tetra word program, double word program, clear status register, program/erase suspend, program/ erase resume, block protect, block unprotect, block lock, protection register program, read configuration register and lock protection pro- gram. status register output may be read at any time, during programming or erase, to monitor the progress of the operation. an internal command interface (c.i.) decodes the instructions while an internal program/erase con- troller (p/e.c.) handles all timing and verifies the correct execution of the program and erase in- structions. p/e.c. provides a status register whose bits indicate operation and exit status of the internal algorithms. the command interface is re- set to read array when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequence must be followed exactly. any invalid combination of commands will reset the device to read array. read (rd) the read instruction consists of one write cycle (refer to device operations section) and places the addressed bank in read array mode. when a device reset occurs, the memory is in read array as default. a read array command will be ignored while a bank is programming or erasing. however in the other bank a read array command will be ac- cepted. read status register (rsr) a bank's status register indicates when a pro- gram or erase operation is complete and the suc- cess or failure of operation itself. issue a read status register instruction (70h) to read the sta- tus register content of the addressed bank. the status of the other bank is not affected by the com- mand. the read status register instruction may be issued at any time, also when a program/erase operation is ongoing. the following read opera- tions output the content of the status register of the addressed bank. the status register is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. read electronic signature (rsig) the read electronic signature instruction con- sists of one write cycle (refer to device operations section) giving the command 90h to an address within the bank a. a subsequent read in the ad- dress of bank a will output the manufacturer code, the device code, the protection status of blocks of bank a, the die revision code, the protection register, or the read configuration register (see table 9). if the first write cycle of read electronic signature instruction is issued to an address within the bank b, a subsequent read in an address of bank b will output the protection status of blocks of bank b. the status of the other bank is not affected by the command (see table 8). see tables 5, 6, 7 and 8 for the valid address. the electronic signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the char- acteristics of m58mr032c and m58mr032d.
m58mr032c, m58mr032d 12/52 table 11. instructions instruction cyc. operation address (1,2) data (3) operation address (1,2) data (3) read rd read memory array 1+ write bka ffh read (1) read address data rsr read status register 1+ write bka 70h read (1) bka status register rsig read electronic signature 1+ write ea 90h read (1) ea ed rcfi read cfi 1+ write ca 98h read (1) ca cd clrs (5) clear status register 1 write bka 50h program/erase ee block erase 2 write ba 20h write ba d0h be bank erase 2 write bka 80h write bka d0h pg program 2 write wa 40h or 10h write wa wd dpg double word program 3 write wa1 30h write wa1 wd1 write wa2 wd2 tpg tetra word program 5 write wa1 55h write wa1 wd1 write wa2 wd2 write wa3 wd3 write wa4 wd4 pes program erase suspend 1 write bka b0h per program erase resume 1 write bka d0h protect bp block protect 2 write ba 60h write ba 01h bu block unprotect 2 write ba 60h write ba d0h bl block lock 2 write ba 60h write ba 2fh configuration prp protection register program 2 write pa c0h write pa pd lprp lock protection register program 2 write lpa c0h write lpa lpd cr write read configuration register 2 write rca 60h write rca 03h
13/52 m58mr032c, m58mr032d cfi query (rcfi) the cfi query mode is associated to bank a. the address of the first write cycle must be within the bank a. the status of the other bank is not affected by the command (see table 8). writing 98h the de- vice enters the common flash interface query mode. next read operations in the bank a will read the cfi data. write a read instruction to return to read mode (refer to the common flash interface section). clear status register (clsr) the clear status register uses a single write op- eration, which resets bits b1, b3, b4 e b5 of the sta- tus register. the clear status register is executed writing the command 50h independently of the ap- plied v pp voltage. after executing this command the device returns to read array mode. the clear status register command clears only the status register of the addressed bank. block erase (ee) block erasure sets all the bits within the selected block to '1'. one block at a time can be erased. it is not necessary to pre-program the block as the p/e.c. will do it automatically before erasing. this instruction use two writes cycles. the first com- mand written is the block erase set up command 20h. the second command is the erase confirm command d0h. an address within the block to be erased should be given to the memory during the two cycles command. if the second command giv- en is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. after writing the command, the device outputs sta- tus register data when any address within the bank is read. at the end of the operation the bank will re- main in read status register until a read array com- mand is written. status register bit b7 is '0' while the erasure is in progress and '1' when it has completed. after com- pletion the status register bit b5 returns '1' if there has been an erase failure. status register bit b1 returns '1' if the user is attempting to erase a pro- tected block. status register bit b3 returns a '1' if v pp is below v pplk . erase aborts if rp turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated (see table 12). a clear status register instruction must be issued to reset b1, b3, b4 and b5 of the status register. during the execution of the erase by the p/e.c., the bank with the block in erase accepts only the rsr (read status regis- ter) and pes (program/erase sus pend) instruc- tions. see figure 19 for erase flowchart and pseudo code. bank erase (be) bank erase sets all the bits within the selected bank to 1. it is not necessary to pre-program the block as the p/e.c. will do it automatically before erasing. this instruction uses two writes cycles. the first command written is the bank erase set-up com- mand 80h. the second command is the erase confirm command d0h. an address within the bank to be erased should be given to the memory during the two cycles command. see the block erase command section for status register bit de- tails. note: 1. first cycle command address should be the same as the operation's target address. the first cycle of the rd, rsr, rsig o r rcfi instruction is followed by read operations in the bank array or special register. any number of read cycles can occur after one com- mand cycle. 2. bka means address within the bank; ba means block address; ea means electronic signature address; ca means common flash interface address; wa means word address; pa means protection register address (see table 7); lpa means lock protection register address (see table 7); rca means read configuration register address. 3. pd means protection data; cd means common flash interface data; ed means electronic signature data; wd means data to be programmed at the address location wa; lpd means lock protection register data 4. wa1, wa2, wa3 and wa4 must be consecutive address differing only for address bits a1-a0. 5. read cycle after e clsr instruction will output the memory array.
m58mr032c, m58mr032d 14/52 table 12. status register bits note: logic level 1 is v ih and 0 is v il . mnemonic bit name logic level definition note p/ecs 7 p/ecs status 1 ready indicates the p/e.c. status, check during program or erase, and on completion before checking bits b4 or b5 for program or erase success. 0 busy ess 6 erase suspend status 1 suspended on an erase suspend instruction p/ecs and ess bits are set to 1. ess bit remains 1 until an erase resume instruction is given. 0 in progress or completed es 5 erase status 1 erase error es bit is set to 1 if p/e.c. has applied the maximum number of erase pulses to the block without achieving an erase verify. 0 erase success ps 4 program status 1 program error ps bit set to 1 if the p/e.c. has failed to program a word. 0 program success vpps 3 v pp status 1 v pp invalid, abort vpps bit is set if the v pp voltage is below v pplk when a program or erase instruction is executed. v pp is sampled only at the beginning of the erase/program operation. 0 v pp ok pss 2 program suspend status 1 suspended on a program suspend instruction p/ecs and pss bits are set to 1. pss remains 1 until a program resume instruction is given. 0 in progress or completed bps 1 block protection status 1 program/erase on protected block, abort bps bit is set to 1 if a program or erase operation has been attempted on a protected block. 0 no operation to protected blocks 0 reserved program (pg) the program instruction programs the array on a word-by-word basis. the first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase sus- pended mode (see table 8). this instruction uses two write cycles. the first command written is the program set-up command 40h (or 10h). a second write operation latches the address and the data to be written and starts the p/e.c. read operations in the targeted bank output the status register content after the programming has started. the status register bit b7 returns '0' while the pro- gramming is in progress and '1' when it has com- pleted. after completion the status register bit b4 returns '1' if there has been a program failure (see table 12). status register bit b1 returns '1' if the user is attempting to program a protected block. status register bit b3 returns a '1' if v pp is below v pplk . any attempt to write a 1 to an already pro- grammed bit will result in a program fail (status register bit b4 set) if v pp = v pph and will be ig- nored if v pp = v pp1 . programming aborts if rp goes to v il . as data in- tegrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. a clear status register instruction must be issued to reset b5, b4, b3 and b1 of the status register. during the execution of the program by the p/e.c., the bank in programming accepts only the rsr (read status register) and pes (program/erase suspend) instructions. see figure 16 for program flowchart and pseudo code.
15/52 m58mr032c, m58mr032d table 13. protection states (1) note: 1. all blocks are protected at power-up, so the default configuration is 001 or 101 according to wp status. 2. current state and next state gives the protection status of a block. the protection status is defined by the write protect in and by dq1 (= 1 for a locked block) and dq0 (= 1 for a protected block) as read in the read electronic signature instruction with a1 = v ih and a0 = v il . 3. next state is the protection status of a block after a protect or unprotect or lock command has been issued or after wp has changed its logic value. 4. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. current state (2) (wp, dq1, dq0) program/erase allowed next state after event (3) protect unprotect lock wp transition 100 yes 101 100 111 000 101 no 101 100 111 001 110 yes 111 110 111 011 111 no 111 110 111 011 000 yes 001 000 011 100 001 no 001 000 011 101 011 no 011 011 011 111 or 110 (4) figure 5. security block memory map ai90023 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 88h 85h 84h 81h 80h
m58mr032c, m58mr032d 16/52 double word program (dpg) this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. the first command must be given to the target block and only one partition can be pro- grammed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see table 8). the two words must differ only for the address a0. programming should not be attempted when v pp is not at v pph . the operation can also be executed if v pp is below v pph but result could be uncertain. these instruction uses three write cycles. the first command written is the double word program set-up command 30h. a second write operation latches the address and the data of the first word to be written, the third write operation latches the address and the data of the second word to be written and starts the p/e.c. (see table 11). read operations in the targeted bank output the status register content after the programming has started. the status register bit b7 returns '0' while the programming is in progress and '1' when it has completed. after completion the status reg- ister bit b4 returns '1' if there has been a program failure. status register bit b1 returns '1' if the user is attempting to program a protected block. status register bit b3 returns a '1' if v pp is below v pplk . any attempt to write a 1 to an already pro- grammed bit will result in a program fail (status register bit b4 set). (see table 12). programming aborts if rp goes to v il . as data in- tegrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. a clear status regis- ter instruction must be issued to reset b5, b4, b3 and b1 of the status register. during the execu- tion of the program by the p/e.c., the bank in pro- gramming accepts only the rsr (read status register) instruction. see figure 17 for double word program flowchart and pseudo code. tetra word program (tpg) this feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel. the first command must be given to the target block and only one partition can be pro- grammed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see table 8). the four words must differ only for the addresses a0 and a1. programming should not be attempted when v pp is not at v pph . the operation can also be executed if v pp is below v pph but result could be uncertain. these instruction uses five write cy- cles. the first command written is the tetra word program set-up command 55h. a second write operation latches the address and the data of the first word to be written, the third write operation latches the address and the data of the second word to be written, the fourth write operation latch- es the address and the data of the third word to be written, the fifth write operation latches the ad- dress and the data of the fourth word to be written and starts the p/e.c. (see table 11). read operations in the targeted bank output the status register content after the programming has started. the status register bit b7 returns '0' while the programming is in progress and '1' when it has completed. after completion the status reg- ister bit b4 returns '1' if there has been a program failure. status register bit b1 returns '1' if the user is attempting to program a protected block. status register bit b3 returns a '1' if v pp is below v pplk . any attempt to write a 1 to an already pro- grammed bit will result in a program fail (status register bit b4 set). (see table 12). programming aborts if rp goes to v il . as data in- tegrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. a clear status regis- ter instruction must be issued to reset b5, b4, b3 and b1 of the status register. during the execu- tion of the program by the p/e.c., the bank in pro- gramming accepts only the rsr (read status register) instruction. see figure 17 for tetra word program flowchart and pseudo code. erase suspend/resume (pes/per) the erase suspend freezes, after a certain laten- cy period (within 25us), the erase operation and al- lows read in another block within the targeted bank or program in the other block. this instruction uses one write cycle b0h and the address should be within the bank with the block in erase (see table 11). the device continues to output status register data after the erase suspend is issued. the status register bit b7 and bit b6 are set to 1 then the erase operation has been sus- pended. bit b6 is set to '0' in case the erase is com- pleted or in progress (see table 12). the valid commands while erase is suspended are: program/erase resume, program, read memory array, read status register, read elec- tronic signature, cfi query, block protect, block unprotect and block lock. the user can protect the block being erased issuing the block protect or block lock commands. during a block erase suspend, the device goes into standby mode by taking e to v ih , which reduc- es active current draw. erase is aborted if rp turns to v il . if an erase suspend instruction was previously ex- ecuted, the erase operation may be resumed by issuing the command d0h using an address within the suspended bank. the status register bit b6 and bit b7 are cleared when erase resumes and read
17/52 m58mr032c, m58mr032d operations output the status register after the erase is resumed. block erase cannot resume until program operations initiated during block erase suspend have completed. it is also possible to nest suspends as follows: suspend erase in the first partition, start programming in the second or in the same partition, suspend programming and then read from the second or the same partition. the suggested flowchart for erase suspend/re- sume features of the memory is shown from fig- ure 20. program suspend/resume (pes/per) program suspend is accepted only during the pro- gram instruction execution. when a program sus- pend command is written to the c.i., the p/e.c. freezes the program operation. program resume (per) continues the program operation. program suspend (pes) consists of writing the command b0h and the address should be within the bank with the word in programming (see table 11). the status register bit b2 is set to '1' (within 5s) when the program has been suspended. bit b2 is set to '0' in case the program is completed or in progress (see table 12). the valid commands while program is suspended are: program/erase resume, read array, read status register, read electronic signature, cfi query. during program suspend mode, the device goes in standby mode by taking e to v ih . this re- duces active current consumption. program is aborted if rp turns to v il . if a program suspend instruction was previously executed, the program operation may be resumed by issuing the command d0h using an address within the suspended bank (see table 11). the status register bit b2 and bit b7 are cleared when program resumes and read operations output the status register after the erase is resumed (see ta- ble 12). the suggested flowchart for program sus- pend/resume features of the memory is shown from figure 18. block protect (bp) the bp instruction use two write cycles. the first command written is the protection set-up 60h. the second command is block protect command 01h, written to an address within the block to be protect- ed (see table 11). if the second command is not recognized by the c.i the bit 4 and bit 5 of the sta- tus register will be set to indicate a wrong se- quence of commands (see table 12). to read the status register write the rsr command. block unprotect (bu) the instruction use two write cycles. the first com- mand written is the protection set-up 60h. the sec- ond command is block unprotect command d0h, written to an address within the block to be protect- ed (see table 11). if the second command is not recognized by the c.i the bit 4 and bit 5 of the sta- tus register will be set to indicate a wrong se- quence of commands (see table 12). to read the status register write the rsr command. block lock (bl) the instruction use two write cycles. the first com- mand written is the protection set-up 60h. the sec- ond command is block lock command 2fh, written to an address within the block to be protect- ed (see table 11). if the second command is not recognized by the c.i the bit 4 and bit 5 of the sta- tus register will be set to indicate a wrong se- quence of commands. to read the status register write the rsr command (see table 12).
m58mr032c, m58mr032d 18/52 block protection the m58mr032c/m58mr032d provide a flexible protection of all the memory providing the protec- tion, un-protection and locking of any blocks. all blocks are protected at power-up. each block of the array has two levels of protection against pro- gramming or erasing operation. the first level is set by the block protect instruction; a protected block cannot be programmed or erased until a block unprotect instruction is given for that block. a second level of protection is set by the block lock instruction, and requires the use of the wp pin, according to the following scheme: C when wp is at v ih , the lock status is overridden and all blocks can be protected or unprotected; C when wp is at v il , lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. blocks that are not locked can still change their protection status; C the lock status is cleared for all blocks at power up. the protection and lock status can be monitored for each block using the read electronic signature (rsig) instruction. protected blocks will output a '1' on dq0 and locked blocks w ill output a '1' in dq1 (see table 13). protection register program (prp) and lock protection register program (lprp) the m58mr032c/m58mr032d features a 128-bit protection register and a security block in order to increase the protection of a system design. the protection register is divided in two 64-bit seg- ments. the first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be programmed by the user. when shipped the user programmable segment is read at '1'. it can be only programmed at '0'. the user programmable segment can be protect- ed writing the bit 1 of the protection lock register (80h). the bit 1 protects also the bit 2 of the pro- tection lock register. the m58mr032c/m58mr032d feature a security block. the security block is located at 1ff000- 1fffff (m58mr032c) or at 000000-000fff (m58mr032d) of the device. this block can be permanently protected by the user programming the bit 2 of the protection lock register (see fig- ure 5). the protection register and the protection lock register can be read using the rsig and rcfi in- structions. a subsequent read in the address start- ing from 80h to 88h, the user will retrieve respectively the protection lock register, the unique device number segment and the otp user programmable register segment (see table 23). write read configuration register (cr). this instruction uses two coded cycles, the first write cycle is the write read configuration regis- ter set-up 60h, the second write cycle is write read configuration register confirm 03h both to read configuration register address (see table 11). this instruction writes the contents of address bits adq15-adq0 to bits cr15-cr0 of the read con- figuration register (a20-a16 are don't care). at power-up the read configuration register is set to asynchronous read mode, power-down dis- abled and bus invert (power save function) dis- abled. a description of the effects of each configuration bit is given in table 14. read mode (cr15). the device supports an asynchronous page mode and a synchronous burst mode. in asynchronous page mode, the de- fault at power-up, data is internally read and stored in a buffer of 4 words selected by adq0 and adq1 address inputs. in synchronous burst mode, the device latches the starting address and then out- puts a sequence of data that depends on the read configuration register settings (see figures 10, 11 and 12). synchronous burst mode is supported in both pa- rameter and main blocks; it is also possible to per- form burst mode read across the banks. bus invert configuration (cr14). this register bit is used to enable the binv pin functionality. binv functionality depends upon configuration bits cr14 and cr15 (see table 14 for configura- tion bits definition) as shown in table 15. as output pin binv is active only when enabled (cr14 = 1) in read array burst mode (cr15 = 0). as input pin binv is active only when enabled (cr14 = 1). binv is ignored when adq0-adq15 lines are used as address inputs (addresses must not be in- verted). x-latency (cr13-cr11). these configuration bits define the number of clock cycles elapsing from l going low to valid data available in burst mode (see figure 6). the correspondence be- tween x-latency settings and the maximum sus- tainable frequency must be calculated taking into account some system parameters. two conditions must be satisfied: C(n + 2) t k 3 t acc + t qvk_cpu + t avk_cpu Ct k > t kqv + t qvk_cpu where "n" is the chosen x-latency configuration code, t k is the clock period, t avk_cpu is the ad- dress setup time guaranteed by the system cpu, and t qvk_cpu is the data setup time required by the system cpu.
19/52 m58mr032c, m58mr032d table 14. read configuration register (as and read cfi instructions) (1) note: 1. the rcr can be read via the rsig command (90h). bank a address + 05h contains the rcr data. see table 9. 2. all the bits in the rcr are set to default on device power-up or reset. table 15. binv configuration bits configuration register function cr15 read mode 0 = synchronous burst mode read 1 = asynchronous page mode read (default) cr14 bus invert configuration (power save) 0 = disabled (default) 1 = enabled cr13-cr11 x-latency 010 = 2 clock latency 011 = 3 clock latency 100 = 4 clock latency 101 = 5 clock latency 111 = reserved other configurations reserved cr10 power-down configuration 0 = power-down disabled (default) 1 = power-down enabled cr9 reserved cr8 wait configuration 0 = wait is active during wait state 1 = wait is active one data cycle before wait state (default) cr7 burst order configuration 0 = interleaved 1 = linear (default) cr6 clock configuration 0 = address latched and data output on the falling clock edge 1 = address latched and data output on the rising clock edge (default) cr5-cr4 reserved cr3 burst wrap 0 = burst wrap within burst length set by cr2-cr0 1 = dont wrap accesses within burst length set by cr2-cr0 (default) cr2-cr0 burst length 001 = 4 word burst length 010 = 8 word burst length 111 = continuous burst mode (requires cr7 = 1) cr15 cr14 binv in out 00x0 0 1 active active 10x0 1 1 active 0
m58mr032c, m58mr032d 20/52 power-down configuration (cr10). the rp pin may be configured to give very low power con- sumption when driven low (power-down state). in power-down the i cc supply current is reduced to a typical figure of i cc2 ; if this function is disabled (default at power-up) the rp pin causes only a re- set of the device and the supply current is the stand-by value. the recovery time after a rp pulse is significantly longer when power-down is en- abled (see table 31). wait configuration (cr8). in burst mode wait indicates whether the data on the output bus are valid or a wait state must be inserted. the config- uration bit determines if wait will be asserted one clock cycle before the wait state or during the wait state (see figure 7). wait is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. burst order configuration (cr7) and burst wrap configuration (cr3). see table 16 for burst order and length. clock configuration (cr6). in burst mode deter- mines if address is latched and data is output on the rising or falling edge of the clock. burst length (cr2-cr0). in burst mode deter- mines the number of words output by the memory. it is possible to have 4 words, 8 words or a contin- uous burst mode, in which all the words are read sequentially. in continuous burst mode the burst sequence can cross the end of each of the two banks (all banks in read array mode). in continu- ous burst mode or in 4, 8 words no-wrap it may happen that the memory will stop the data output flow for a few clock cycles; this event is signaled by wait going low until the output flow is resumed. the initial address determines if the output delay will occur as well as its duration. if the starting ad- dress is aligned to a four words boundary no wait states will be needed. if the starting address is shifted by 1,2 or 3 positions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence is crossing the first 64 word boundary. wait will be asserted only once during a continuous burst access. see also table 16. figure 6. x-latency configuration sequence ai90024 a20-a16 valid address k l adq15-adq0 valid address valid data valid data adq15-adq0 valid address valid data adq15-adq0 valid address valid data valid data valid data configuration code 4 configuration code 3 conf. code 2 valid data valid data valid data
21/52 m58mr032c, m58mr032d figure 7. wait configuration sequence ai90025 a20-a16 valid address k l adq15-adq0 valid address valid data wait cr8 = '0' wait cr8 = '1' valid data not valid valid data
m58mr032c, m58mr032d 22/52 table 16. burst order and length configuration mode starting address 4 words 8 words continuous burst linear interleaved linear interleaved wrap 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... ... 60 60-61-62-63-64-65-66... 61 61-62-63-wait-64-65-66... 62 62-63-wait-wait-64-65-66... 63 63-wait-wait-wait-64-65-66... linear interleaved linear interleaved no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7... 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5-6-7-8... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9... ... 7 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13... ... 60 60-61-62-63 60-61-62-63-64-65-66-67 60-61-62-63-64-65-66... 61 61-62-63-wait-64 61-62-63-wait-64-65-66-67-68 61-62-63-wait-64-65-66... 62 62-63-wait-wait-64-65 62-63-wait-wait-64-65-66-67-68-69 62-63-wait-wait-64-65-66... 63 63-wait-wait-wait-64-65-66 63-wait-wait-wait-64-65-66-67-68-69-70 63-wait-wait-wait-64-65-66...
23/52 m58mr032c, m58mr032d power consumption power-down the memory provides reset/power-down control input rp . the power-down function can be acti- vated only if the relevant read configuration reg- ister bit is set to '1'. in this case, when the rp signal is pulled at v ss the supply current drops to typically i cc2 (see table 26), the memory is dese- lected and the outputs are in high impedance. if rp is pulled to v ss during a program or erase op- eration, this operation is aborted and the memory content is no longer valid (see reset/power-down input description). power-up the memory command interface is reset on pow- er-up to read array. either e or w must be tied to v ih during power-up to allow maximum security and the possibility to write a command on the first rising edge of w . at power-up the device is config- ured as: C page mode: (cr15 = 1) C power-down disabled: (cr10 = 0) C binv disabled: (cr14 = 0). all blocks are protected and unlocked. v dd , v ddq and v pp are independent power sup- plies and can be biased in any order. supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v dd rails decoupled with a 0.1f capac- itor close to the v dd , v ddq and v ss pins. the pcb trace widths should be sufficient to carry the re- quired v dd program and erase currents.
m58mr032c, m58mr032d 24/52 common flash interface (cfi) the common flash interface (cfi) specification is a jedec approved, standardized data structure that can be read from the flash memory device. cfi allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. cfi allows the system to easily interface to the flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. tables 17, 18, 19, 20, 21, 22 and 23 show the ad- dress used to retrieve each data. the cfi data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. the cfi data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. this area can be accessed only in read mode and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode (see table 11). refer to the cfi query instruction to understand how the m58mr032 enters the cfi query mode. table 17. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 18, 19, 20, 21, 22 and 23. query data are always presented on the lowest order data outputs. table 18. cfi query identification string note: query data are always presented on the lowest - order data outputs (adq0-adq7) only. adq8-adq15 are 0. 1. drc means die revision code. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 80h security code area lock protection register unique device number and user programmable otp offset sub-section name description value 00h 0020h manufacturer code st 01h 88dah 88dbh device code top bottom 02h reserved reserved 03h drc (1) die revision code 04h-0fh reserved reserved 10h 0051h query unique ascii string "qry" "q" 11h 0052h "r" 12h 0059h "y" 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0039h address for primary algorithm extended query table (see table 20) p = 39h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) na 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table (0000h means none exists) na 1ah 0000h
25/52 m58mr032c, m58mr032d table 19. cfi query system interface information offset data description value 1bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 1dh 0017h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 1eh 00c0h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 12v 1fh 0004h typical timeout per single byte/word program = 2 n s 16s 20h 0004h typical timeout for tetra word program = 2 n s 16s 21h 000ah typical timeout per individual block erase = 2 n ms 1s 22h 0000h typical timeout for full chip erase = 2 n ms na 23h 0004h maximum timeout for word program = 2 n times typical 512s 24h 0004h maximum timeout for tetra word = 2 n times typical 512s 25h 0004h maximum timeout per individual block erase = 2 n times typical 16s 26h 0000h maximum timeout for chip erase = 2 n times typical na
m58mr032c, m58mr032d 26/52 table 20. device geometry definition offset word mode data description value 27h 0016h device size = 2 n in number of bytes 4 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 byte 2ch 0003h number of erase block regions within the device bit 7 to 0 = x = number of erase block regions it specifies the number of regions within the device containing one or more contiguous erase blocks of the same size. 3 m58mr032c 2dh 2eh 002fh 0000h region 1 information (main block - bank b) number of identical-size erase block = 002fh+1 48 2fh 30h 0000h 0001h region 1 information (main block - bank b) block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 000eh 0000h region 2 information (main block - bank a) number of identical-size erase block = 000eh+1 15 33h 34h 0000h 0001h region 2 information (main block - bank a) block size in region 2 = 0100h * 256 byte 64 kbyte 35h 36h 0007h 0000h region 3 information (parameter block - bank a) number of identical-size erase block = 0007h+1 8 37h 38h 0020h 0000h region 3 information (parameter block - bank a) block size in region 3 = 0020h * 256 byte 8 kbyte m58mr032d 2dh 2eh 0007h 0000h region 1 information (parameter block - bank a) number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information (parameter block - bank a) block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 000eh 0000h region 2 information (main block - bank a) number of identical-size erase block = 000eh+1 15 33h 34h 0000h 0001h region 2 information (main block - bank a) block size in region 2 = 0001h * 256 byte 64 kbyte 35h 36h 002fh 0000h region 3 information (parameter block - bank b) number of identical-size erase block = 002fh+1 48 37h 38h 0000h 0001h region 3 information (parameter block - bank b) block size in region 3 = 0001h * 256 byte 64 kbyte
27/52 m58mr032c, m58mr032d table 21. primary algorithm-specific extended query table offset data description value (p)h = 39h 0050h primary algorithm extended query table unique ascii string pri "p" 0052h "r" 0049h "i" (p+3)h = 3ch 0031h major version number, ascii "1" (p+4)h = 3dh 0030h minor version number, ascii "0" (p+5)h = 3eh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 9 simultaneous operation supported (1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are 0. if bit 31 is 1 then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h 0000h (p+8)h 0000h (p+9)h = 42h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 ye s (p+a)h = 43h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register protect/unprotect bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 ye s ye s (p+b)h 0000h (p+c)h = 45h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8v (p+d)h = 46h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12v (p+e)h = 47h (p+f)h (p+10)h (p+11)h (p+12)h 0000h reserved
m58mr032c, m58mr032d 28/52 table 22. burst read information table 23. security code area offset data description value (p)+13h = 48h 0003h page-mode read capability bits 0-7 n such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. 8 byte (p+14)h = 49h 0003h number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 3 (p+15)h = 4ah 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+16)h = 4bh 0002h synchronous mode read capability configuration 2 8 (p+17)h = 4ch 0007h synchronous mode read capability configuration 3 cont. (p+18)h = 4dh 0028h max operating clock frequency (mhz) 40 mhz (p+19)h = 4eh 0001h supported handshaking signal (wait pin) bit 0 during synchronous read (1 = yes, 0 = no) bit 1 during asynchronous read (1 = yes, 0 = no) ye s no offset data description 80h 0000-0000-0000-0xx0 lock protection register 81h xxxx 64 bits: unique device number 82h xxxx 83h xxxx 84h xxxx 85h xxxx 64 bits: user programmable otp 86h xxxx 87h xxxx 88h xxxx
29/52 m58mr032c, m58mr032d figure 9. ac testing load circuit ai90027 v ddq / 2 out c l = 30pf c l includes jig capacitance 3.3k w 1n914 device under test table 24. ac measurement conditions input rise and fall times 4ns input pulse voltages 0 to v ddq input and output timing ref. voltages v ddq /2 figure 8. testing input/output waveforms ai90026 v ddq 0v v ddq /2 table 25. capacitance (1) (t a = 25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
m58mr032c, m58mr032d 30/52 table 26. dc characteristics (t a = C40 to 85c; v dd = v ddq = 1.7v to 2.0v) note: 1. sampled only, not 100% tested. 2. v pp may be connected to 12v power supply for a total of less than 100 hrs. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i cc1 supply current (asynchronous read mode) e = v il , g = v ih , f = 6mhz 10 20 ma supply current (synchronous read mode continuous burst) e = v il , g = v ih , f = 40mhz 20 30 ma i cc2 supply current (power-down) rp = v ss 0.2v 210a i cc3 supply current (standby) e = v dd 0.2v 15 50 a i cc4 (1) supply current (program or erase) word program, block erase in progress 10 20 ma i cc5 (1) supply current (dual bank) program/erase in progress in one bank, asynchronous read in the other bank 20 40 ma program/erase in progress in one bank, synchronous read in the other bank 30 50 ma i pp1 v pp supply current (program or erase) v pp = 12v 0.6v 510ma i pp2 v pp supply current (standby or read) v pp v cc 0.2 5 a v pp = 12v 0.6v 100 400 a v il input low voltage C0.5 0.4 v v ih input high voltage v ddq C0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = C100a v ddq C0.1 v v pp1 v pp supply voltage program, erase v ddq C0.4 v ddq + 0.4 v v pph v pp supply voltage double/tetra word program 11.4 12.6 v v pplk program or erase lockout 1 v
31/52 m58mr032c, m58mr032d table 27. asynchronous read ac characteristics (t a = C40 to 85c; v dd = v ddq = 1.7v to 2.0v) note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . symbol alt parameter test condition m58mr032 unit 100 120 min max min max t avav t rc address valid to next address valid e = v il , g = v il 100 120 ns t avlh t avavdh address valid to latch enable high g = v ih 10 10 ns t av qv t acc address valid to output valid (random) e = v il , g = v il 100 120 ns t av qv 1 t pa ge address valid to output valid (page) e = v il , g = v il 45 45 ns t ehqx t oh chip enable high to output transition g = v il 00ns t ehqz (1) t hz chip enable high to output hi-z g = v il 20 20 ns t ellh t elavdh chip enable low to latch enable high e = v il , g = v ih 10 10 ns t elqv (2) t ce chip enable low to output valid g = v il 100 120 ns t elqx (1) t lz chip enable low to output transition g = v il 00ns t ghqx t oh output enable high to output transition e = v il 00ns t ghqz (1) t df output enable high to output hi-z e = v il 20 20 ns t glqv (2) t oe output enable low to output valid e = v il 25 35 ns t glqx (1) t olz output enable low to output transition e = v il 00ns t lhax t avd hax latch enable high to address transition e = v il , g = v ih 10 10 ns t lhgl latch enable high to output enable low e = v il 10 10 ns t lllh t avdlavdh latch enable pulse width e = v il , g = v ih 10 10 ns t llqv t avdlqv latch enable low to output valid (random) e = v il 100 120 ns t llqv1 latch enable low to output valid (page) e = v il 45 45 ns
m58mr032c, m58mr032d 32/52 figure 10. asynchronous read ac waveforms ai90028 tavav tavqv telqx tehqx tglqv tglqx tghqx adq0-adq15 e g telqv valid address tehqz tghqz valid data valid address a16-a20 valid address valid address l tellh tllqv tlllh tavlh tlhax tlhgl note: write enable (w ) = high.
33/52 m58mr032c, m58mr032d figure 11. page read ac waveforms ai90029 tavqv1 tglqv tghqz adq0-adq15 e g telqv valid address a16-a20 valid address l tllqv valid address valid data valid address valid data valid data valid address valid data tllqv1 tavlh tlhax tlhgl
m58mr032c, m58mr032d 34/52 table 28. synchronous burst read ac characteristics (t a = C40 to 85c; v dd = v ddq = 1.7v to 2.0v) symbol alt parameter test condition m58mr032 unit 100 120 min max min max t avk t avclkh address valid to clock 7 7 ns t elk t celclkh chip enable low to clock 7 7 ns t k t clk clock period 25 25 ns t kax t clkhax clock to address transition e = v il , g = v ih 13 13 ns t khkl t clkhclkl clock high 5 5 ns t klkh t clklclkh clock low 5 5 ns t kqv t clkhqv clock to data valid clock to binv valid clock to wait valid e = v il , g = v il 20 20 ns t kqx t clkhqx clock to output transition clock to binv transition clock to wait transition e = v il 44ns t lhax t advhax latch enable high to address transition 13 13 ns t llk t avdlclkh latch enable low to clock 7 7 ns
35/52 m58mr032c, m58mr032d figure 12. synchronous burst read ai90030 adq0-adq15 e g a16-a20 l binv wait k valid address valid valid valid valid address tlllh tavlh tglqx tavk tllk telk tkax tkqx tkqv valid data valid valid valid note 1 note 2 note 3 tkqv tkqv tehqx tehqz tghqx tghqz tk tkqx tkqx note: 1. the number of clock cycles to be inserted depends upon the x-latency set in the read configuration register. 2. wait signal can be configured to be active during wait state or one cycle below wait state. 3. wait signal is asserted only when burst length is configured as continuous (see burst read section for further information).
m58mr032c, m58mr032d 36/52 table 29. write ac characteristics, write enable controlled (t a = C40 to 85 c; v dd = v ddq = 1.7v to 2.0v) symbol alt parameter m58mr032 unit 100 120 min max min max t avav t wc address valid to next address valid 100 120 ns t avlh address valid to latch enable high 10 10 ns t dvwh t ds input valid to write enable high 40 40 ns t ellh chip enable low to latch enable high 10 10 ns t elwl t cs chip enable low to write enable low 0 0 ns t ghll output enable high to latch enable low 20 20 ns t ghwl output enable high to write enable low 20 20 ns t lhax latch enable high to address transition 10 10 ns t lhwh latch enable high to write enable high 10 10 ns t lllh latch enable pulse width 10 10 ns t vdhel t vcs v dd high to chip enable low 50 50 s t vpphwh v pp high to write enable high 200 200 ns t whdx t dh write enable high to input transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl t oeh write enable high to output enable low 0 0 ns t whll write enable high to latch enable low 0 0 ns t whvppl write enable high to v pp low 200 200 ns t whwl t wph write enable high to write enable low 30 30 ns t whwpv write enable high to write protect valid 200 200 ns t wlwh t wp write enable low to write enable high 50 50 ns t wpvwh write protect valid to write enable high 200 200 ns
37/52 m58mr032c, m58mr032d figure 13. write ac waveforms, w controlled ai90031 tlhax adq0-adq15 l g tavlh data valid address valid a16-a20 e tlllh telwl tghwl w address valid tdvwh twhdx twlwh tellh tghll twhgl v dd tvdhel binv valid tlhwh twhll wp twpvwh twhwpv v pp tvpphwh v pp1 v pph twhvppl tavav valid
m58mr032c, m58mr032d 38/52 table 30. write ac characteristics, chip enable controlled (t a = C40 to 85 c; v dd = v ddq = 1.7v to 2.0v) symbol alt parameter m58mr032 unit 100 120 min max min max t avav t wc address valid to next address valid 100 120 ns t avlh address valid to latch enable high 10 10 ns t dveh t ds input valid to chip enable high 40 40 ns t ehdx t dh chip enable high to input transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehwh t wh chip enable high to write enable high 0 0 ns t eleh t cp chip enable low to chip enable high 60 60 ns t ellh chip enable low to latch enable high 10 10 ns t ghll output enable high to latch enable low 20 20 ns t lhax latch enable high to address transition 10 10 ns t lheh latch enable high to chip enable high 10 10 ns t lllh latch enable pulse width 10 10 ns t vdhel t vcs v dd high to chip enable low 50 50 s t vppheh v pp high to chip enable high 200 200 ns t ehvppl chip enable high to v pp low 200 200 ns t ehwpv chip enable high to write protect valid 200 200 ns t wlel t ws chip enable low to chip enable low 0 0 ns t wpveh write protect valid to chip enable high 200 200 ns
39/52 m58mr032c, m58mr032d figure 14. write ac waveforms, e controlled tlhax adq0-adq15 l g tavlh data valid address valid a16-a20 e tlllh teleh w address valid tdveh tehdx tehwh tellh tghll binv valid tlheh twlel ai90032 v dd tvdhel wp twpveh tehwpv v pp tvppheh v pp1 v pph tehvppl tehel valid
m58mr032c, m58mr032d 40/52 figure 15. reset and power-up ac waveforms ai90033 w, v dd , v ddq tplph e, g tphwl tphel tphgl tphwl tphel tphgl tvdhph rp l, power-up table 31. reset and power-up ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 100ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or system reset. table 32. program, erase times and program, erase endurance cycles (t a = C40 to 85c; v dd = v ddq = 1.7v to 2.0v, v pp = v dd unless otherwise specified) note: 1. max values refer to the maximum time allowed by the internal algorithm before error bit is set. worst case conditions pr ogram or erase should perform significantly better. 2. excludes the time needed to execute the sequence for program instruction. 3. same timing value if v pp = 12v. symbol parameter test condition min unit t plph (1,2) rp pulse width 100 ns t phel t phll t phwl reset high to device enabled during program and erase 50 s other conditions 30 ns t vdhph (3) supply valid to reset high 50 s parameter min max (1) typ typical after 100k w/e cycles unit parameter block (4 k-word) erase (preprogrammed) 2.5 0.5 1 sec main block (32 k-word) erase (preprogrammed) 10 1 3 sec bank erase (preprogrammed, bank a) 4 sec bank erase (preprogrammed, bank b) 15 sec chip program (2) 40 sec chip program (dpg, v pp = 12v) (2) 20 sec word program (3) 200 10 10 s double word program 200 10 10 s tetra word program 200 10 10 s program/erase cycles (per block) 100,000 cycles
41/52 m58mr032c, m58mr032d figure 16. program flowchart and pseudo code (1) note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a program sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 40h or 10h command ai90034 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program instruction: C write 40h or 10h command C write address & data (memory enters read status state after the program instruction) do: C read status register (e or g must be toggled) if pes instruction given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: C error handler suspend suspend loop no yes
m58mr032c, m58mr032d 42/52 figure 17. double word program and tetra word program flowchart and pseudo code (1) note: 1. status check of b1 (protected block), b3 (vpp invalid) and b4 (program error) can be made after each program operation o r after a program sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 3. address 1 and address 2 must be consecutive addresses differing only for address bit a0. 4. address, address 2, address 3 and address 4 must be consecutive addresses differing only for address bit a1-a0. write 55h command ai90035 start write address 1 & data 1 read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) dpg instruction: C write 30h command C write address 1 & data 1 (3) C write address 2 & data 2 (3) (memory enters read status state after the program instruction) do: C read status register (e or g must be toggled) if pes instruction given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4 = 1, program error: C error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: C error handler suspend suspend loop no yes write address 2 & data 2 write address 3 & data 3 write address 4 & data 4 tpg instruction: C write 55h command C write address 1 & data 1 (4) C write address 2 & data 2 (4) C write address 3 & data 3 (4) C write address 4 & data 4 (4) (memory enters read status state after the program instruction)
43/52 m58mr032c, m58mr032d figure 18. program suspend & resume flowchart and pseudo code write 70h command ai90036 read status register yes no b7 = 1 yes no b2 = 1 program continues write a read command pes instruction: C write b0h command do: C read status register (e or g must be toggled) while b7 = 1 if b2 = 0 program completed write d0h command per instruction: C write d0h command to resume the program C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued). read data from another address start write b0h command program complete write ffh command read data
m58mr032c, m58mr032d 44/52 figure 19. block erase flowchart and pseudo code write 20h command ai90037 start write block address & d0h command read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error (1) ee instruction: C write 20h command C write block address (a12-a20) & command d0h (memory enters read status state after the ee instruction) do: C read status register (e or g must be toggled) if pes instruction given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler end yes no b1 = 0 erase to protected block error (1) if b1 = 1, erase to protected block error: C error handler yes
45/52 m58mr032c, m58mr032d figure 20. erase suspend & resume flowchart and pseudo code write 70h command ai90038 read status register yes no b7 = 1 yes no b6 = 1 erase continues pes instruction: C write b0h command do: C read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed write d0h command read data from another block or program/protection program or block protect/unprotect/lock start write b0h command erase complete write ffh command read data per instruction: C write d0h command to resume erasure C if the erase operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued).
m58mr032c, m58mr032d 46/52 table 33. command interface states - lock table current state of the other partition current state of the current partition command input to the current partition (and next state of the current partition) mode state others read memory array (ffh) erase confirm p/ e resume bu confirm (d0h) read status register (70h) clear status register (50h) read elect. sign. (90h) read cfi (98h) block protect- unprotect- lock setup write rcr setup (60h) block protect confirm (01h) block lock confirm (2fh) write rcr confirm (03h) any state read array see modi fy table read array read array read status register read array read el ect. si gn. read cfi block protect- unprotect- locksetup wri te rcr setup read array read array read array cfi electronic signature status any state protect unprotect lock rcr setup bl ock protect- unprotect- lockerror wri t e rcr error bl ock protect- unprotect- lockerror wr it e rcr error block protect- unprotect- lockblock block protect- unprotect- lockerror writ e rcr error block protect- unprotect- lockerror writ e rcr error block protect- unprotect- lockerror writ e rcr error block protect- unprotect- lockerror writ e rcr error block protect- unprotect- lockerror wri te rcr error block protect- unprotect- lockblock bl ock protect- unprotect- lockblock set rcr error see modi fy table read array read array read status register read array read el ect. si gn. read cfi block protect- unprotect- locksetup wri te rcr setup read array read array read array protect- unprotect- lockblock set rcr any state protection register done see modi fy table read array read array read status register read array read el ect. si gn. read cfi block protect- unprotect- locksetup wri te rcr setup read array read array read array any state program- multiple program done see modi fy table read array read array read status register read array read el ect. si gn. read cfi block protect- unprotect- locksetup wri te rcr setup read array read array read array setup program suspend read array, cfi, elect. sign., status see modi fy table ps read array program (busy) ps read status register ps read array ps read el ect. si gn. ps read cfi ps read array ps read array ps read array ps read array idle erase suspend idle block-bank erase setup erase error erase error erase (busy) erase error erase error erase error erase error erase error erase error erase error erase error any state error see modi fy table read array read array read status register read array read el ect. si gn. read cfi block protect- unprotect- locksetup wri te rcr setup read array read array read array done setup erase suspend read array, cfi, elect. sign., status see madify table es read array erase (busy) es read status register es read array es read el ect. si gn. es read cfi block protect- unprotect- locksetup wri te rcr setup es read array es read array es read array busy es read array idle erase (busy) program suspend es read array
47/52 m58mr032c, m58mr032d table 34. command interface states - modify table current state of the other partition current state of the current partition command input to the current partition (and next state of the current partition) mode state others program setup (10h/40h) block erase setup (20h) program-erase suspend (b0h) otp setup (c0h) multiple program setup (30h/55h) bank erase setup (80h) setup read array, cfi, electronic signature, status register see lock table read array read array read array read array read array read array busy idle program setup block erase setup otp setup multiple program setup bank erase setup erase suspend read array read array read array program suspend read array read array setup protect unprotect-lock/ rcr error, protect- unprotect- lockblock, set rcr see lock table read array read array read array read array read array read array busy idle program setup block erase setup otp setup multiple program setup bank erase setup erase suspend read array read array read array program suspend read array read array idle protection regi st er setup protection register (busy) protection register (busy) protection register (busy) protection register (busy) protecti on register (busy) protection register (busy) protection register (busy) setup busy busy done see lock table read array read array read array read array read array read array idle program setup block erase setup otp setup multiple program setup bank erase setup erase suspend read array read array read array program suspend read array read array any state program- multiple program setup program (busy) program (busy) program (busy) program (busy) program (busy) program (busy) program (busy) idle busy ps read status register setup done see lock table read array read array read array read array read array read array busy idle program setup block erase setup otp setup multiple program setup bank erase setup erase suspend read array read array read array program suspend read array read array setup program suspend read array, cfi, elect. sign., status regi st er see lock table ps read array ps read array ps read array ps read array ps read array ps read array idle erase suspend idle block-bank erase setup see lock table erase error erase error erase error erase error erase error erase error busy erase (busy) erase (busy) erase (busy) es read status register erase (busy) erase (busy) erase (busy) setup erase suspend read array, cfi, elect. sign., status regi st er see lock table es read array es read array es read array es read array es read array es read array busy idl e program setup multiple program setup program suspend es read array es read array
m58mr032c, m58mr032d 48/52 table 35. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. table 36. daisy chain ordering scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m58mr032c 100 zc 6 t device type m58 architecture m = multiplexed address/data, dual bank, burst mode operating voltage r = 1.8v device function 032c = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, top boot 032d = 32 mbit (x16), dual bank: 1/4-3/4 partitioning, bottom boot speed 100 = 100 ns 120 = 120 ns package zc = tfbga48: 0.5 mm pitch temperature range 6 = C40 to 85c option t = tape & reel packing example: m58mr032 -zc t device type m58mr032 daisy chain -zc = tfbga48: 0.5 mm pitch option t = tape & reel packing
49/52 m58mr032c, m58mr032d table 37. document revision history date version revision details november 2000 -01 first issue 12/20/00 -02 protection/security clarification fbga connections change (figure 2) memory map diagram clarification (figure 3) single synchronous read clarification (figure 4) identifier codes clarification (table 9) x-latency configuration clarification cfi query identification string change (table 18) synchronous burst read waveforms change (figure 12) reset ac characteristics clarification (table 31) program time clarification (table 32) tfbga package mechanical and outline drawing change (table 27, figure 21) 1/08/01 -03 reset ac characteristics clarification (table 31) reset ac waveforms diagram change (figure 15) 3/02/01 -04 document type: from target specification to product preview write ac waveforms w contr. change (figure 13) reset and power-up ac characteristics and waveform change (table 31, figure 15) tfbga package mechanical data change (table 38) 3/19/01 -05 tfbga package mechanical data change reset and power-up ac characteristics clarification 01-aug-2002 5.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 05 becomes 5.0). supply voltage ranges v dd and v ddq modified, burst mode read frequency modified. maximum operating frequency modified in table 22, burst read information. parameters t k , t kqv , t kax and t lhax modified in table 28, synchronous burst read ac characteristics. document status changed from product preview to preliminary data.
m58mr032c, m58mr032d 50/52 table 38. tfbga48 - 10 x 4 ball array, 0.5 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 0.950 1.200 0.0374 0.0472 a1 0.200 0.300 0.0079 0.0118 a2 0.790 0.0311 b 0.300 0.250 0.350 0.0118 0.0098 0.0138 d 10.530 10.480 10.580 0.4146 0.4126 0.4165 d1 4.500 C C 0.1772 C C d2 6.500 C C 0.2559 C C d3 8.500 C C 0.3346 C C ddd 0.080 0.0031 e 6.290 6.240 6.340 0.2476 0.2457 0.2496 e1 1.500 C C 0.0591 C C e2 3.500 C C 0.1378 C C e3 5.500 C C 0.2165 C C e 0.500 C C 0.0197 C C fd 3.015 C C 0.1187 C C fd1 2.015 C C 0.0793 C C fd2 1.015 C C 0.0400 C C fe 2.395 C C 0.0943 C C fe1 1.395 C C 0.0549 C C fe2 0.395 C C 0.0156 C C sd 0.250 C C 0.0098 C C se 0.250 C C 0.0098 C C figure 21. tfbga48 - 10 x 4 ball array, 0.5 mm pitch, bottom view package outline drawing is not to scale. a2 a1 bga-z17 dummy balls d d1 e fd2 fd1 b e e1 ddd e3 d3 sd se fe a ball "a1" e2 d2 fd fe1 fe2
51/52 m58mr032c, m58mr032d figure 22. tfbga48 daisy chain - package connections (top view through package) figure 23. tfbga48 daisy chain - pcb connections proposal (top view through package) ai90039 h g 6 5 4 3 d c e f a b 12 78 13 12 11 10 914 end point start point ai90040 h g 6 5 4 3 d c e f a b 12 78 13 12 11 10 914
m58mr032c, m58mr032d 52/52 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unite d states. www.st.com

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